1. Field of the Invention
The present invention relates to a CMOS integrated circuit, and more particularly, it relates to a CMOS integrated circuit mixedly provided with a silicified transistor and a non-silicified transistor.
2. Description of Related Art
A CMOS (Complementary Metal Oxide Semiconductor) integrated circuit has advantages such as small power consumption and a stable operation, and is widely applied to a VLSI (Very Large Scale Integrated Circuit). In recent years, a CMOS integrated circuit mixedly provided with transistors of different types has also been implemented.
For example, a CMOS integrated circuit in which part of transistors are silicide transistors and the other transistors are non-silicide transistors is implemented. In this integrated circuit, the silicide transistors exhibiting low gate, source and drain resistance values of about 15Ω can be utilized as transistors for high-speed operations, while the non-silicide transistors having excellent withstand voltage characteristics against external surge voltages, for example, can be utilized as input/output circuits to which high electrostatic withstand voltages are required. Therefore, a semiconductor integrated circuit chip mixedly provided with the different types of silicide transistors and non-silicide transistors can be used for various applications.
A conventional method of manufacturing a CMOS integrated circuit mixedly provided with silicide transistors and non-silicide transistors generally performs first an NSD step of forming source and drain regions for N-type transistors after forming gate electrodes on the surface of a silicon substrate, then a PSD step of forming source and drain regions for P-type transistors, and thereafter a step of covering the non-silicide transistors with oxide films and forming silicide films on the gate electrodes, the source regions and the drain regions of silicified transistors.
In this case, As+ (arsenic) ions are implanted in the NDS step in order to form the N-type source and drain regions, while the implanted As+ ions may punch through the gate electrodes. In order to prevent this, an oxide film (TEOS film, for example) having a thickness of about 180 Å must be deposited in advance of the NSD step, and the deposited TEOS film is removed with hydrofluoric acid after the NSD step.
When the transistors are selectively silicified, the non-silicified transistors must be covered with protective oxide films (TEOS films, for example). The silicifying step is carried out while depositing TEOS films having a thickness of about 500 Å, for example, on the non-silicide transistors. Therefore, the TEOS films must be removed by etching with hydrofluoric acid after the silicifying step.
As hereinabove described, the conventional method inevitably includes two steps of removing oxide films with hydrofluoric acid. In the steps of removing the oxide films by etching with hydrofluoric acid, isolation oxide films (STI oxide films, for example) are excessively scraped off due to overetching, to result in increase in borderless contact leakage.
The present invention has been proposed under the aforementioned circumstances, and a main object of the present invention is to provide a CMOS integrated circuit capable of ensuring a leakage margin for preventing increase in borderless contact leakage.
Another object of the present invention is to provide an improved CMOS integrated circuit mixedly provided with a silicide transistor and a non-silicide transistor.
Further another object of the present invention is to provide a method of manufacturing a CMOS integrated circuit reducing a hydrofluoric acid treatment step for removing an oxide film.